In many cases the data processing speed of a computer system can be greatly enhanced by providing one or more additional processors to form a multiprocessor system in which a common or central RAM memory is shared. However, the sharing of resources, particularly the memory, results in conflicts between the processors' various memory reference requests, such that if the memory, memory paths, and the memory access control logic is not properly designed much of the potential increase in efficiency and economy of the system can be lost to access delays.
Minimizing conflicts and delays in accessing a shared memory is typically accomplished in two different but cooperative ways. One way is to segment the shared memory into many independently addressable banks such that each reference to a bank ties up a relatively small percentage of the memory, leaving the rest of the memory accessible. Segmenting memory, however, increases the complexity and thus size and cost can also impose limitations on the speed at which each reference may be accomplished.
Memory reference delays can also be managed and minimized through careful design of the memory pathways between the processors and the addressable banks in the memory, and of the conflict resolution circuits which arbitrate conflicting memory requests. As may be readily appreciated, the design of this "memory interface" and the design of the memory organization are interrelated and interdependent.
Ideally, the memory interface should provide for maximum utilization of the available memory access paths such that each processor has substantially equal accessibility to the memory at most times, particularly where there is no master-salve relationship between the processors. In addition, it is desireable that memory access conflicts be resolved in as few system clock periods as possible so that reference start up time and data buffering requirements are held to a minimum. The attainment of these goals is, however, restrained by the cost and particularly the quantity of logic which may be employed. In particular, in the case of high-speed vector processing machines there are tight restrictions on the space which may be allotted to interface circuits due to the necessity to bring all processors into close proximity to the memory in order that propagation delays be minimized. In addition, it is desireable that logic and wiring requirements be held down.
As is well appreciated by those skilled in the art, attaining an efficient, economical and workable memory interface becomes increasingly difficult as the number of processors is increased. Those designs which may be quite efficient in a dual or four processor system may be totally unsuitable for systems with more processors because of the increases in logic which are needed to adapt such schemes to a larger number of processors, and the additional demands made on the memory by the additional processors. Moreover, increasing the number of processors typically increases the nominal distance between a given processor and the memory, increasing signal propagation delay and placing further restraints on the number of logic levels which may be employed.
Accordingly, it is readily seen that the system used to share memory in a multiprocessor system is crucial to its efficiency. Moreover, it is readily seen that there are not only a large number of constraints on the design of such systems but in addition that these constraints often work against one another to present a difficult design challenge.